H. Peter Hofstee, Jun Sawada
Information Processing Letters
Paper
Synergistic processing in cell's multicore architecture
Abstract
Eight synergistic processor units enable the Cell Broadband Engine's breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar and SIMD processing on a wide data path. A large number of SPUs per chip provide high thread-level parallelism. © 2006 IEEE.
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