Conference paper
Optimizing compiler for a CELL processor
Alexandre E. Eichenberger, Kathryn O'Brien, et al.
PACT 2005
Paper
Synergistic processing in cell's multicore architecture
Abstract
Eight synergistic processor units enable the Cell Broadband Engine's breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar and SIMD processing on a wide data path. A large number of SPUs per chip provide high thread-level parallelism. © 2006 IEEE.
Related
Kemal Ebcioglu, Erik Altman, et al.
IEEE TC
Conference paper
Optimizing pipelines for power and performance
Viji Srinivasan, David Brooks, et al.
MICRO 2002
Steven C. Chan, Phillip J. Restle, et al.
IEEE Journal of Solid-State Circuits