Vertical interconnect technology for enlarging capacity on micro solid thin film rechargeable battery
- Akihiro Horibe
- Kuniaki Sueoka
- et al.
- 2019
- ECTC 2019
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54 results for Hiroyuki Mori
Solder Injected through Via for Multi Stacked Wafers
- Akihiro Horibe
- Kuniaki Sueoka
- et al.
- 2016
- ECTC 2016
Novel Low Cost Bumping Process with Non-strip Type Photosensitive Resin and Injection Molded Solder (IMS) for Fine Pitch Flip Chip Joining
- Toyohiro Aoki
- Takashi Hisada
- et al.
- 2016
- ECTC 2016
Proposal of Package Structure Requirements for Effective Cooling from the Bottom Side of Chips (from the Substrate Side), Aiming for a Three-Dimensional (3D) Chip Stack
- Keiji Matsumoto
- Hiroyuki Mori
- 2016
- ECTC 2016
Through silicon via process for effective multi-wafer integration
- Akihiro Horibe
- Kuniaki Sueoka
- et al.
- 2015
- ECTC 2015
Dual-side cooling for a three-dimensional (3D) chip stack : Additional cooling from the laminate (substrate) side
- Keiji Matsumoto
- Hiroyuki Mori
- et al.
- 2015
- ECTC 2015
Wafer-level non conductive films for exascale servers
- Akihiro Horibe
- Sayuri Kohara
- et al.
- 2014
- ECTC 2014
Thermally enhanced pre-applied underfills for 3D integration
- Akihiro Horibe
- Keishi Okamoto
- et al.
- 2013
- ECTC 2013
No Clean Flux technology for large die flip chip packages
- Akihiro Horibe
- Kang-Wook Lee
- et al.
- 2013
- ECTC 2013
CFD Simulation Analysis of Inter/Intra Chip Liquid Cooling for 3D Stacked ICs
- Risa Miyazawa
- Hiroyuki Mori
- et al.
- 2023
- iTHERM 2023