About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
IRPS 2023
Conference paper
Write-error-rate of Spin-Transfer-Torque MRAM (Invited)
Abstract
Embedded Spin-Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) is now a standard foundry offering for embedded non-volatile memory applications at the 28 nm node and below, where it replaces embedded Flash, due to lower development costs. The switch from in-plane to perpendicularly magnetized magnetic materials enabled reliable operation and a scaling path. Write-error-rate is the key reliability challenge for STT-MRAM. While due to fundamental physics, write-error-rate of STT-MRAM can be engineered to meet even aggressive product specifications.