Quinn Pham, Danila Seliayeu, et al.
CASCON 2024
We consider the problem of implementing a wait-free regular register from storage components prone to Byzantine faults. We present a simple, efficient, and self-contained construction of such a register. Our construction utilizes a novel building block, called a 1-regular register, which can be efficiently implemented from Byzantine fault-prone components. © 2006 Elsevier B.V. All rights reserved.
Quinn Pham, Danila Seliayeu, et al.
CASCON 2024
B. Wagle
EJOR
Hendrik F. Hamann
InterPACK 2013
Preeti Malakar, Thomas George, et al.
SC 2012