Thomas M. Cover
IEEE Trans. Inf. Theory
We consider the problem of implementing a wait-free regular register from storage components prone to Byzantine faults. We present a simple, efficient, and self-contained construction of such a register. Our construction utilizes a novel building block, called a 1-regular register, which can be efficiently implemented from Byzantine fault-prone components. © 2006 Elsevier B.V. All rights reserved.
Thomas M. Cover
IEEE Trans. Inf. Theory
John M. Boyer, Charles F. Wiecha
DocEng 2009
Preeti Malakar, Thomas George, et al.
SC 2012
Leo Liberti, James Ostrowski
Journal of Global Optimization