Chidanand Apté, Fred Damerau, et al.
ACM Transactions on Information Systems (TOIS)
We consider the problem of implementing a wait-free regular register from storage components prone to Byzantine faults. We present a simple, efficient, and self-contained construction of such a register. Our construction utilizes a novel building block, called a 1-regular register, which can be efficiently implemented from Byzantine fault-prone components. © 2006 Elsevier B.V. All rights reserved.
Chidanand Apté, Fred Damerau, et al.
ACM Transactions on Information Systems (TOIS)
Nanda Kambhatla
ACL 2004
Limin Hu
IEEE/ACM Transactions on Networking
Khaled A.S. Abdel-Ghaffar
IEEE Trans. Inf. Theory