Conference paper
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
Jean-Olivier Plouchart, Mark A. Ferriss, et al.
CICC 2012
A W-band balanced frequency doubler with an optimized harmonic termination and neutralization technique is proposed for high output power and high conversion efficiency in a 90-nm SiGe process. The proposed design demonstrates a peak conversion gain of 0.7 dB and the maximum output power higher than 4 dBm at an output frequency of 84 GHz with the conversion efficiency of 14%.
Jean-Olivier Plouchart, Mark A. Ferriss, et al.
CICC 2012
Bodhisatwa Sadhu, Arun Paidimarri, et al.
IEEE JSSC
Shlomo Shlafman, David Goren, et al.
COMCAS 2011
Keith A. Jenkins, Yu-Ming Lin, et al.
ECS Transactions