VLSI routing methodology for quadrupole metal sea-of-cells design

Abstract

The authors present a general sea-of-cells routing methodology for the most advanced VLSI technology today, where four layers of metal are available for signal interconnection. As routing channels are defined over the cells, the entire chip can be fully populated with circuit cells. The routing process starts with multi-layer global routing, followed by vertical line packing and horizontal channel routing. The global wires are converted to pseudo pins in the vertical channel, and horizontal channels are completed by using a novel four-layer channel router.