Advanced bipolar technology for the 1990s

Abstract

The advent of low temperature epitaxy processes provides a new degree of freedom for bipolar device scaling. This paper describes new vertical scaling concepts and process technology elements required for advanced scaled bipolar (NPN and PNP) devices which will be the core of high-performance application-specific bipolar, BiCMOS, or complementary bipolar/BiCMOS logic and memory chips. In particular, the authors address key issues such as transit time reduction by SiGe base band-gap engineering, junction field/capacitance control by using lightly-doped emitter (LDE) and collector (LDC) concepts, lateral scaling (reduction of parasitic R and C) by advanced self-aligned structures and trench isolations, and liquid-nitrogen temperature (LNT) operation. Challenges for future BiCMOS and complementary bipolar/BiCMOS process technologies are examined.