Publication
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Paper

VLSI Layout Compaction with Grid and Mixed Constraints

View publication

Abstract

We investigate the modeling and solution techniques of VLSI layout compaction using the constraint graph approach under various practical design considerations. In particular, we extend the graph method to the compaction of VLSI layout with mixed grid constraints in addition to the usual minimum- and maximum-type constraints. This is a mixed integer problem. We show that it can be solved by the search of effectively longest paths, and a fast algorithm is presented. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.

Date

01 Jan 1987

Publication

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors

Share