Taming pattern and focus variation in VLSI design
Fook-Luen Heng, Puneet Gupta, et al.
AMM 2004
We investigate the modeling and solution techniques of VLSI layout compaction using the constraint graph approach under various practical design considerations. In particular, we extend the graph method to the compaction of VLSI layout with mixed grid constraints in addition to the usual minimum- and maximum-type constraints. This is a mixed integer problem. We show that it can be solved by the search of effectively longest paths, and a fast algorithm is presented. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.
Fook-Luen Heng, Puneet Gupta, et al.
AMM 2004
Donald T. Tang, C.N. Liu
IEEE TC
Jin Fuw Lee, Donald T. Tang, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Donald T. Tang, Chin-Long Chen
IEEE TC