Understanding stress gradients in microelectronic metallization

Abstract

The manufacture of ultra-large scale integration technology can impose significant strain within the constituent metallization because of the mismatch in coefficients of thermal expansion between metallization and its surrounding environment. The resulting stress distributions can be large enough to induce voiding within Cu-based metallization, a key reliability issue that must be addressed. The interface between the Cu and overlying capping layers is a critical location associated with void formation. By combining conventional and glancing-incidence X-ray diffraction, depth-dependent stress distributions that develop in Cu films and patterned features are investigated. In situ annealing and as-deposited measurements reveal that strain gradients are created in capped Cu structures, where an increased in-plane tensile stress is generated near the Cu/cap interface. The interplay between plasticity in Cu and the constraint imposed by capping layers dictates the extent of the observed gradients. Cu films possessing caps deposited at temperatures where Cu experienced only elastic deformation did not exhibit depth-dependent stress distributions. However, all capped Cu samples exposed to temperatures that induce plastic behavior developed greater tensile stress at the Cu/cap interface than in the bulk Cu film after cooling, representing a clear concern for the mitigation of metallization voiding.© 2012 JCPDS-ICDD.