Publication
IEEE T-ED
Paper

Transport and Related Properties of (Ga, Al)As/GaAs Double Heterostructure Bipolar Junction Transistors

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Abstract

This paper presents a study of the transport and related properties of Ga As double heterostructure bipolar junction transistors with GaAlAs emitters and collectors utilizing both graded and abrupt junctions. By studying the temperature dependence of current-voltage characteristics, the recombination mechanisms in the transition regions associated with the base-emitter, the base-collector junction, and the quasi-neutral base region have been quantitatively separated. The junction corresponding to growth of GaAs on GaAlAs is found to have higher nonradiative recombination. For abrupt junctions, it also shows a lower barrier for electron injection than does the GaAlAs/GaAs junction. At mid-1018 cm-3 base doping, the junctions show ideal emission/diffusion transport at high currents, recombination-dominated transport in a medium current range, and transport with a characteristic energy greater than twice the thermal energy at very low currents. Due to excess recombination current in the devices, the offset voltage is shown to be sensitive to the ratio of emitter and collector junction areas. At low temperatures, transport across the injecting interface of abrupt devices is dominated by tunneling and in the quasi-neutral base by diffusion. The devices exhibit gain at temperatures as low as 4.2 K. The current gain below 77 K appears to be limited by radiative recombination lifetime, and at higher temperatures by nonradiative recombination and injection efficiency. Transistors with current gains of 300 to 500 have been achieved at small emitter dimensions of 1.6 μm, x 4.0 μm and at current densities exceeding 10s A.cm-2. At current densities of 100 A.cm-2, some of the transistors exhibited gains approaching 100. These devices had an offset voltage of less than 100 mV. Self-aligned devices have also been fabricated and show current gains of 20 to 50 at similar dimensions. In the inverted configuration, gains of up to 50 were observed for non-self-aligned transistors. The dependence of device characteristics upon the structure indicates that surface effects are minimal. The negative resistance exhibited by these devices at high currents is shown to be due to temperature effects resulting from the 10-ps or lower thermal time constants. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.

Date

01 Jan 1987

Publication

IEEE T-ED

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