Transistor Matching and Fin Angle Variation in FinFET Technology

Abstract

The introduction of FinFET architecture was expected to alleviate the issue of mismatch compared with planar technology, given the lower doping levels required. However, several authors have reported better mismatch results for planar technology suggesting additional challenges for FinFET architecture. An additional mechanism previously not considered arising from charge present at points of disturbance in the silicon lattice in tapering and wavering fins is shown to contribute to transistor mismatch. We show that including this mechanism improves the quantitative understanding of mismatch in FinFETs.