Nanda Kambhatla
ACL 2004
We present an efficient method for tolerating faults in a two-dimensional mesh architecture. Our approach is based on adding spare components (nodes) and extra links (edges) such that the resulting architecture can be reconfigured as a mesh in the presence of faults. We optimize the cost of the fault-tolerant mesh architecture by adding about one row of redundant nodes in addition to a set of k spare nodes (while tolerating up to k node faults) and minimizing the number of links per node. Our results are surprisingly efficient and seem to practical for small values of k. The degree of the fault-tolerant architecture is k + 5 for odd k, and k+6 for even k. Our results can be generalized to d-dimensional meshes. © 1994.
Nanda Kambhatla
ACL 2004
Alessandro Morari, Roberto Gioiosa, et al.
IPDPS 2011
A. Gupta, R. Gross, et al.
SPIE Advances in Semiconductors and Superconductors 1990
György E. Révész
Theoretical Computer Science