Technologies to further reduce soft error susceptibility in SOI

Methods for soft error rate reduction in silicon on insulator devices and circuits are explored and evaluated via simulations that have been validated against hardware measurements. Our methodology is first introduced, and the following techniques are examined in detail: 1) Body thinning, 2) carrier lifetime reduction, 3) body contacts, 4) stacked devices, and 5) parallel devices. Finally, the advantages and disadvantages of all methods are described. © 2009 IEEE.