64-bit prefix adders: Power-efficient topologies and design solutions

Abstract

64-bit adders of various prefix algorithms are designed using a novel dataflow synthesis methodology, Our synthesis methodology offers robust adder solutions typically used for high-performance microprocessor needs. We have analyzed the power-performance tradeoffs for a portfolio of popular adder topologies and design styles. In particular, the intrinsically sparser designs in hierarchical prefix scheme are demonstrated to be preferable choices for both high-performance and low-power adder applications. © 2009 IEEE.