We report a new approach to building an ASIC-style superconducting SFQ logic cell library for the 8-layer 0.35 μm Niobium SFQ5ee process from MIT LL. The developed library layout template supports XY routing with Passive Transmission Lines (PTLs) and targets conventional Place-and-Route assembly for the design of VLSI Random Logic Macros (RLMs). The designed library gates are based on clockless Dynamic SFQ (DSFQ) logic which allows one to directly implement deep combinational logic clouds. The full library gates communicate only via an XY PTL routing plane, while internally they are assembled from smaller self-contained subgates, connected via inductors and placed in one template row. We report test results for two chips that independently verify library subgate assemblies that are used to build DSFQ logic gates as well as active PTL interconnect; on-chip testbenches provide low-speed and high-speed (GHz) test modes. We have achieved low-speed and high-speed functionality of both the DSFQ logic gates (AND, OR, and AO21) and active interconnect circuitry (transmitters Tx and receivers Rx) used for communicating SFQ signals over 700 μm PTLs and short (∼50 μm) series inductor-resistor (LR) connections. The measured speed of the OR and AND logic circuits exceeded 10 GHz, while the speed for PTLs and LR connections was more than 10 and 30 GHz, respectively.