IEDM 1999
Conference paper

Sub-60 nm physical gate length SOI CMOS


This work addresses the design and optimization of high performance CMOS devices in the sub-60 nm regime. Aggressive scaling of the poly gate length is achieved by controlling the short-channel effects in partially-depleted SOI CMOS devices. A high performance SOI CMOS with well-behaved 52 nm gate length devices is demonstrated.