Publication
IEEE Transactions on VLSI Systems
Paper

SRAM write-ability improvement with transient negative bit-line voltage

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Abstract

Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without using any on-chip or off-chip negative voltage source. Statistical simulations in a 45nm PD/SOI technology show a 103 X} reduction in the Write-failure probability with the proposed method. © 2006 IEEE.

Date

01 Jan 2011

Publication

IEEE Transactions on VLSI Systems

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