SPT CELL - A NEW SUBSTRATE - PLATE TRENCH CELL FOR DRAMS.

Abstract

A new trench-capacitor DRAM cell has been demonstrated in an advanced, 3. 3-V n-well CMOS technology with the fabrication of functional, fully decoded 64-K arrays. This cell is superior to previously reported trench cells because the storage node is inside the trench and the transfer device is fabricated in an n-well. Most of the storage capacitance is between the polysilicon filling the trench and the grounded p** plus substrate. Fully decoded, 64-K bit arrays with a cell size of 22 mu m **2 have been successfully operated at 3. 3 V. Cell yields greater than 99% have been observed. Operating and signal levels are in agreement with model predictions.