Publication
ECTC 2022
Conference paper

Solder and Organic Adhesive Hybrid Bonding Technology with Non-strip Type Photosensitive Resin and Injection Molded Solder (IMS)

Abstract

For system performance improvement, heterogeneous integration (HI) has widely been recognized to realize high speed and high band-width communication between different kinds of chips (e.g., CPUs, GPUs and memory chips). For HI, chip-to-wafer or chip-to-chip bonding is required. Cu and SiO2 hybrid bonding has been studied for wafer-to-wafer applications [1-3], and recently, for chip-to-wafer and chip-to-chip applications [4,5]. It requires special treatments or special tools, such as cleaning of the surface, vacuum environment, high bonding pressure, high bonding or annealing temperature. On the other hand, solder and organic adhesive hybrid bonding is another candidate for chip-to-wafer and chip-to-chip applications. It does not require any special tools, and a conventional thermal compression bonder (a flip chip bonder) can be used. One of technical challenges of solder and organic adhesive hybrid bonding in fine pitch, such as 20micron pitch or 10micron pitch, is that compressed (deformed) solder may result in short circuit (bridge) between adjacent interconnects, because solder becomes liquid-phase and organic adhesive’s modulus becomes low at bonding temperature such as 250℃. Also, when non conductive paste (NCP) is used as organic adhesive, filler or paste entrapment occurs during the bonding which results in the reliability degradation under electro-migration. To solve these challenges, in this study, we propose novel solder and organic adhesive hybrid bonding technology, based on Injection Molded Solder (IMS) with non-strip type photosensitive resin (resist) [6] and unique thin adhesive. Conventional resist (strip-type) is stripped away after IMS, but the non-strip type resist is not stripped away and used as permanent resist. In IMS, molten solder is injected into fine pitch cavities which are made in resist on a wafer. By using non-strip type resist (permanent resist), the resist can be used for IMS bumping mask and encapsulation after chip joining. This process is suitable for fine pitch, because there is no undercut issue of seed-layer etching during electroplating. Also, cured permanent resist works as spacers and it prevents for solder bumps to be deformed too much and short circuits between adjacent interconnects are avoided. The permanent resist does not have good adhesion, therefore another adhesive material is required to interconnect between a chip (diced from a wafer) and a substrate (such as a chip or a wafer). A unique thin adhesive is used for this method. After the adhesive is cured at 200℃, it is tack-less, but is bondable to SiO2 and polyimide at bonding temperature above 200℃. For a wafer of top chips, the proposed process mainly comprises three steps. As the first step, permanent resist is patterned on a wafer, cured, and then IMS is performed. As the second step, thin adhesive is spin-coated on fabricated solder bumps and permanent resist. As the third step, chemical mechanical polishing (CMP) is performed to remove redundant adhesive on solder bumps, and solder bumps and adhesive are planarized. Also by CMP, solder bump top surface is exposed, therefore there is no concern of filler or paste entrapment. CMP is indispensable to realize coplanarity between solder bumps and adhesive and to eliminate the risk of filler or paste entrapment, even though CMP takes some cost. The resulting encapsulation material is a two-layer-structure of cured permanent resist and thin adhesive. For a substrate, a dielectric material, such as polyimide, is patterned. Then, metal, such as Ni and Au, are electroless-plated in patterned cavities and metal pads are fabricated. By this process, metal pad top surface and dielectric top surface are controlled to be as flat as possible. The ultimate goal is to apply the proposed process to 10-20micron pitch interconnects. However, as the early phase of the process development, we perform a series of process steps required for 10-20micron interconnects using 80micron pitch and 40micron pitch test vehicles (TVs). We also conduct reliability evaluations under thermal cycling (from -55℃ to 125℃), temperature humidity bias (85℃, RH 85%, 3.7V), and high temperature storage (150℃). There are no critical issues in this early demonstration and it supports that by further process optimization, this solder and organic adhesive hybrid bonding can be extendable to 20micron pitch or 10micron pitch. [1] Shigetou et al., IEEE Trans. Adv. Packaging, pp.218-226, 2006 [2] Léa Di Cioccio et al., Handbook of Wafer Bonding, pp. 237-259, 2012 [3] Kagawa et al., IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM), R01, pp. 1-3, 2018 [4] Gao et al., International Wafer-Level Packaging Conference, 2019 [5] Gao et al., International Wafer-Level Packaging Conference, 2020 [6] Aoki et al., IEEE ECTC, pp. 413-419, 2016

Date

30 May 2022

Publication

ECTC 2022

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