ISSCC 1996
Conference paper

Single-chip 4×500Mbaud CMOS transceiver


A CMOS chip is presented that replaces a 72-wire interface with 4 serial, duplex links, for relief of interconnect congestion in applications such as large switching systems. The design supports transmission at 1.6Gb/s per direction in full-duplex mode and provides the user with a transparent interface. The data source provides fixed-length synchronous packets segmented into 4 parallel bytes along with parity and flag bits. The packet size can be programmed up to 4×64B with a parameter loaded from an external controller. Data packets can be transmitted contiguously. During idle periods that are marked by a flag, the circuit generates and transmits fill packets, which start with a non-data Comma character. The Comma marks both byte and packet boundaries on a serial link. The Fill packets carry an idle sequence or diagnostic and control information. A block diagram of the chip shows that each link carries 400Mb/s, corresponding to 500Mbaud after 8B/0B encoding.