Abstract
The integration level of silicon VLSI has been increasing approximately 4X every three years for memory chips and approximately 2X every two years for logic chips. CMOS technology, with its unique negligible-standby-power characteristics, is ideally suited for continuing these trends in integration. The integration levels, as well as the practical circuit speeds, of bipolar are severely constrained by the large standby power of bipolar circuits. CMOS is scalable to about 0.15μm for room temperature applications, and to smaller than 0.1μm for low-temperature applications. Furthermore, CMOS on ultra-thin SOI could be 2X as fast as bulk CMOS. In addition to emphasis on low power dissipation, there will be emphasis on 3D structures, stacked multi-layer ICs, and planarized multi-level fine-pitch and variable-width interconnect technology.