R. Scheuerlein, W.J. Gallagher, et al.
ISSCC 2000
A 12.5 Gb/s and a 9.95 Gb/s fully monolithic SiGe BiCMOS 3.3V clock and data recovery (CDR) circuits were described. They were developed for SONET OC-192 and 10GBE applications. Two different loops, one for frequency acquisition and other for data recovery were used. The small pull-in range of a PLL in data recovery caused the requirement of frequency-acquistion. A delay interpolating ring oscillator was used in each circuit.
R. Scheuerlein, W.J. Gallagher, et al.
ISSCC 2000
M. Soyuer, J.N. Burghartz, et al.
BCTM 1996
H. Ainspan, C. Webster
Electronics Letters
M. Khater, J.-S. Rieh, et al.
IEDM 2004