Hans Jacobson, Alper Buyuktosunoglu, et al.
HPCA 2011
Early stage modeling of processor reliability is a key feature in the design and manufacturing cycle of IBM server-class processors. In this paper, we present SERMiner, a highly adaptable methodology for early-stage processor reliability estimation. We demonstrate how this methodology can be used to evaluate potential processor vulnerability to soft errors. We carry out extensive evaluations to determine the vulnerability across a comprehensive suite of synthetic and real-world benchmarks and also show how this estimation evolves across different processor generations and stages of design.
Hans Jacobson, Alper Buyuktosunoglu, et al.
HPCA 2011
Jingwen Leng, Alper Buyuktosunoglu, et al.
MICRO 2015
Zishen Wan, Nandhini Chandramoorthy, et al.
DAC 2023
Zishen Wan, Karthik Swaminathan, et al.
ICCAD 2022