Power consumption has become a major consideration in nanometer chip design. Since the dynamic power is proportional to Vdd2, and the static power is proportional to Vdd, lowering power supply voltage is an efficient method to reduce the power usage. In this paper, we adopt the row-based dual-supply voltage (DSV) scheme. DSV assigns a low power supply voltage to timing noncritical gates for the power saving. Contrary to the traditional regionbased voltage island works, the row-based approach creates voltage islands along the circuit rows. This kind of fine grid voltage islands give more flexibility on gate voltage assignment such that the low voltage gates can be selected primarily based on timing and design logic, which in turn minimizes the shifter insertion. We present a two-stage flow to generate voltage islands for every two mirrored circuit rows and place gates legally inside each island. To the best of our knowledge, this is also the first work to cover latch and LCB (local clock buffer) handling and shifter placement in voltage island generation. The experimental results demonstrate the effectiveness and efficiency of our approach. Copyright 2014 ACM.