Robust level converter design for sub-threshold logic

Abstract

The large supply voltage difference between sub-threshlold core logic and I/O makes it extremely challenging to convert signals from core circuit to I/O circuit. In this paper, we propose two novel circuits, Clock Synchronizer and Reduced Swing Inverter to design dynamic and static level converters for sub-threshold logic. Circuit simulations shows that our level converters work at frequency > 500Khz between 20°C and 40°C with a supply voltage of 0.25V. Copyright 2006 ACM.