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JES
Paper

RIE Contamination of Etched Silicon Surfaces

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Abstract

A study of RIE contamination of blanket-etched silicon surfaces was initiated to ensure that the use of RIE is compatible with VLSI applications. Contamination is of greater concern as device dimensions shrink because full dry etching in critical process steps is required to control the smaller dimensions. Silicon surfaces were blanket etched in CF4, CF4 + O2, and CF4 + H2. The RIE contamination was characterized by incorporating the etched silicon surface into MOS capacitors. The MOS retention time was measured to detect the presence of fast-diffusing heavy metals in the silicon, and the dielectric breakdown defect density of the oxide was calculated to evaluate the quality of the etched surface. Small amounts of heavy metals on the RIE cathode resulted in poor MOS retention time in etched silicon wafers. However, the stainless steel walls and grounded surfaces are not sources of contamination in an RIE reactor. The silicon surfaces were roughened microscopically when etched on a metal substrate holder. The surface roughness resulted in a lower average breakdown field of the thermally grown oxide. The effect of pre- and post-RIE process steps is discussed as well as the significance of the data to the processing of FET’s. © 1982, The Electrochemical Society, Inc. All rights reserved.

Date

09 Dec 2019

Publication

JES

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