RFCMOS technology from 0.25μm to 65nm: The state of the art

Abstract

The effort to design RF circuits in CMOS is motivated by low cost and significant capacity for on-chip integration. We discuss some of the challenges of implementing RF designs in CMOS focusing on those introduced by the changing properties of FETs as technology nodes scale and devices shrink. We present methods and tools using which designers can ease these challenges and reduce the risk of implementing RF circuits in CMOS. ©2004 IEEE.