Learning Reduced Order Dynamics via Geometric Representations
Imran Nasim, Melanie Weber
SCML 2024
A generic process for fabricating a vertical surround-gate field-effect transistor (VS-FET) based on epitaxially grown silicon nanowires was discussed. The silicon nanowires used were epitaxially grown by chemical vapor deposition (CVD) on a (111)-oriented p-type silicon substrate. It was found that the bending of the nanowire was probably due to stress during the spin-on-glass coating step and/or the polyimide curing. The results show that the array of VS-FET exhibited a gate-voltage-dependent current increase of more than two orders of magnitude.
Imran Nasim, Melanie Weber
SCML 2024
E. Babich, J. Paraszczak, et al.
Microelectronic Engineering
Andreas C. Cangellaris, Karen M. Coperich, et al.
EMC 2001
Kenneth R. Carter, Robert D. Miller, et al.
Macromolecules