New device architectures such as horizontal Nanosheets have been seriously considered as a replacement for FinFET. A comprehensive, and realistic assessment of these architectures at the early stages of technology development is indispensable to understand their value propositions. In this study a new holistic technology-evaluation methodology for an early technology assessment is proposed. This methodology closely links performance-power metrics to realistic area scaling using block area assessment. This is especially critical for lower track cells since routing complexity can severely degrade performance. In addition, the optimization of an M1 power staple design combined with this evaluation can provide 12% additional area reduction with less than 1% of inverter performance penalty.