Superconducting qubit based systems have made tremendous strides in device performance, from improved coherences to lowered single- and two-qubit gate errors, and high-fidelity mid-circuit measurements and qubit resets. In this talk, I will present recent progress towards fault tolerant quantum error correction on superconducting qubit systems, that leverages the resources from improved device performance. I will focus on experimental demonstrations on a heavy-hexagon topology, an arrangement that reduces lattice connectivity compared to other popular low-degree parity-check codes in order to mitigate cross-talk between fixed-frequency transmon qubits. I will describe some of the encoding, syndrome extraction, and decoding operations that can be tailored to this topology, focusing on d = 2 and 3 codes. The code design, along with the current level of hardware noise, place this system in a very favorable path for the coming years in the quest for scalable, fault-tolerant quantum error correction. Our results and preliminary simulations highlight not only the versatility and flexibility of the underlying heavy-hexagon topology, but also the importance of tailoring a decoder when implementing these protocols. *We acknowledge support from IARPA under Contract No. W911NF-16-1-0114.