Publication
IEEE Journal of Solid-State Circuits
Paper

Power Partition and Emitter Size Optimization for Bipolar ECL Circuit

View publication

Abstract

This paper describes an automated approach for optimizing the performance of bipolar ECL circuit. A quadratic equation representing an approximate surface is used to express the circuit delay in terms of the power partition and current densities in the current-switch and the emitter-follower stages. During the iteration of the optimization process, the optimal obtained from the present approximate surface is used as the new nominal point for the next iteration. As the nominal point converges to the optimal, the approximate surface converges to a section of the real optimum surface. This methodology transforms the circuit optimization into a multivariable optimization problem and is shown to provide an optimum design with circuit analysis accuracy. The design considerations of high-performance ECL circuits are also discussed. © 1993 IEEE.

Date

Publication

IEEE Journal of Solid-State Circuits

Authors

Share