PMOSFET-based ESD protection in 65nm bulk CMOS technology for improved external latchup robustness

Abstract

We present for the first time an ESD protection strategy using silicide-blocked PMOSFETs to improve negative-mode external latchup robustness by eliminating N+ junctions directly connected to the I/O pad. 100ns TLP data of thin (Tox=1.25nm) and thick oxide (Tox=5.2nm) silicide-blocked PMOSFETs in a 65nm CMOS technology show failure currents of ∼6mA/μm and ∼5mA/μm respectively, suitable for on-chip ESD protection.