Phase edge lithography for sub 0.1 μm electrical channel length in a 200 MM full CMOS process

Abstract

In this work a deep-UV stepper is used in conjunction with a phase edge mask to define sub 0.1 μm electrical channel length gates in a 200mm integrated CMOS process. Conventional binary intensity mask deep-UV and mid-UV lithography are used for other levels. We demonstrate excellent channel length control with the phase edge technique, at channel lengths here-to-fore only achievable by e-beam or x-ray lithography.