VLSI Technology 1990
Conference paper

Perimeter and plug effects in deep sub-micron polysilicon emitter bipolar transistors

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The scaling limits of nonplanar polysilicon emitters are studied by fabricating and measuring NPN transistors with emitter depths between 10 nm and 25 nm, with emitter widths down to 0.2 μm, and with an epitaxial base as narrow as 50 nm. Excellent device characteristics can be achieved for an emitter depth of 25 nm. Transistors with shallower emitters are degraded by an arsenic depletion at the emitter perimeter and by plugging of the polysilicon in very narrow emitters. The dopant depletion at the perimeter for wide and plugged emitters has been verified by energy-dispersive X-ray spectroscopy (EDX) measurements. Additional rapid thermal annealing (RTA) gives more uniform dopant distribution and a nondegraded transistor with a 0.2 μm-wide, 20 nm-deep poly emitter. It is thought desirable to scale down the emitter poly thickness, to reduce the emitter topography, or to use in situ doping in order to overcome the perimeter and plug effects in very narrow bipolar transistors. © 1990 IEEE.