PERFORMANCE OF HETEROSTRUCTURE FET'S IN LSI.

Abstract

A comparative evaluation is presented of circuits based on heterostructure field-effect transistors (HFETs) for delay, noise margin, and power dissipation in unloaded and loaded configurations. Comparisons are made of n-channel enhancement/depletion (E/D) circuits operating at 300 and 77 K and complementary circuits operating at 77 K. The author also shows that a modified short-channel MOSFET model gives good agreement with experimental behavior of the devices and is adequate for evaluation. Fan-in (FI) sensitivities of delay are much smaller than fan-out (FO) sensitivities of delay for E/D circuits because of capacitive effects. E/D circuit delays are more fan-out sensitive at 300 K than at 77 K because of lower current capability. The fan-in sensitivity of the delay of complementary circuits is larger and is comparable to that circuit's fan-out sensitivity. Under loaded conditions (FI is 3, FO is 3, capacitance is 0. 1 pF) at 77 K, the 0. 5- mu m gate length E/D structure shows gate delays near 50 ps and the 1. 0- mu m gate length shows gate delays near 75 ps.