An analytic MOST model has been developed to calculate accurately threshold voltage at submicrometer dimensions and to predict the scaling limits of digital CMOS circuits. Salient results show that for 2-V power-supply voltages, channel lengths as small as 0.14 µm for static E/E CMOS, 0.20 µm for static E/D CMOS, 0.29 µm for dynamic transmission-gate CMOS, and 0.45 µm for static E/D NMOS circuits are possible. At submicrometer dimensions, CMOS offers as much as a 3:1 scaling advantage in minimum channel length which translates to a 5:1 improvement in gate delay when compared to NMOS. Thus CMOS is projected as the dominant ULSI technology, not only due to its well known large operating margins, low static-power dissipation and design flexibility but also due to markedly superior speed. Copyright © 1985 by The Institute of Electrical and Electronics Engineers, Inc.