Conference paper
High performance SOI/Cu SRAMs and memories in microprocessors
R.V. Joshi, S.S. Kang, et al.
AMC 2001
An ECL circuit with a charge-buffered active-pull-down emitter-follower stage is described. Implemented in a 0-8 /an double-poly trench-isolated selfaligned bipolar process, unloaded gate delays of 14.9ps/2.2mW, 20.7ps/1.2mW, and 24.5ps/0.77mW have been achieved. © 1992, The Institution of Electrical Engineers. All rights reserved.
R.V. Joshi, S.S. Kang, et al.
AMC 2001
J. Warnock, J. Keaty, et al.
IBM J. Res. Dev
Keith A. Jenkins, J.D. Cressler, et al.
IEDM 1991
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Physical Review B - CMMP