C.T. Chuang, P.F. Lu, et al.
VLSI-TSA 1997
Paper
14.9 ps/2.2 mW charge-buffered active-pull-down ECL circuit
Abstract
An ECL circuit with a charge-buffered active-pull-down emitter-follower stage is described. Implemented in a 0-8 /an double-poly trench-isolated selfaligned bipolar process, unloaded gate delays of 14.9ps/2.2mW, 20.7ps/1.2mW, and 24.5ps/0.77mW have been achieved. © 1992, The Institution of Electrical Engineers. All rights reserved.
Related
R.M. Rao, J. Kim, et al.
SOI 2007
D.D. Awschalom, J. Warnock
Physical Review B
X. Liu, A. Petrou, et al.
Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films