J. Warnock, J.D. Cressler, et al.
IEEE Electron Device Letters
An ECL circuit with a charge-buffered active-pull-down emitter-follower stage is described. Implemented in a 0-8 /an double-poly trench-isolated selfaligned bipolar process, unloaded gate delays of 14.9ps/2.2mW, 20.7ps/1.2mW, and 24.5ps/0.77mW have been achieved. © 1992, The Institution of Electrical Engineers. All rights reserved.
J. Warnock, J.D. Cressler, et al.
IEEE Electron Device Letters
D.D. Awschalom, J. Warnock, et al.
QELS 1989
C.T. Chuang, R.M. White
IEEE Electron Device Letters
C.T. Chuang, J.D. Cressler, et al.
Electronics Letters