J. Warnock, J.Y.-C. Sun, et al.
IEEE T-ED
Paper
14.9 ps/2.2 mW charge-buffered active-pull-down ECL circuit
Abstract
An ECL circuit with a charge-buffered active-pull-down emitter-follower stage is described. Implemented in a 0-8 /an double-poly trench-isolated selfaligned bipolar process, unloaded gate delays of 14.9ps/2.2mW, 20.7ps/1.2mW, and 24.5ps/0.77mW have been achieved. © 1992, The Institution of Electrical Engineers. All rights reserved.
Related
C.T. Chuang, Ken Chin, et al.
CICC 1992
Satish Kumar, Rajiv V. Joshi, et al.
ICICDT 2007
Conference paper
Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM
R.V. Joshi, C.T. Chuang, et al.
VLSI Technology 2001