Christophe R. Tretz, C.T. Chuang, et al.
IEEE International SOI Conference 1998
'Tapered gate' is a device sizing methodology to improve the performance of critical paths in stacked circuit configurations. This paper presents a detailed study of the performance leverage of tapered gate in a partially depleted silicon-on-insulator (PD/SOI) technology. It is shown that the reduced junction capacitance in a PD/SOI device renders the series resistance reduction of the lower transistors in the stack more effective. The effects are also shown to be more pronounced for low-VT cases. The study demonstrates that tapered gate remains a viable device sizing technique/methodology for improving performance in a PD/SOI technology.
Christophe R. Tretz, C.T. Chuang, et al.
IEEE International SOI Conference 1998
Satish Kumar, Rajiv V. Joshi, et al.
ICICDT 2007
T.C. Chen, J.D. Cressler, et al.
VLSI Technology 1989
Rajiv V. Joshi, Richard Q. Williams, et al.
ESSDERC/ESSCIRC 2004