Experimental 27 ns 1 Mb CMOS high-speed DRAM
S. Dhong, W.H. Henkels, et al.
VLSI Circuits 1989
This paper presents a general signal and layout analysis for the two-transistor, one-capacitor DRAM cell. The 2T, 1C configuration enables significantly larger, typically > 3×, raw sense-signal than is achievable in conventional IT, 1C cells. In general, stray capacitances at the capacitor nodes further increase the signal level; an exact analytic formula is derived in this case, including the dependence upon bitline precharge level. With trench technology, the 2T, 1C cell occupies 25-30% more area than a corresponding folded-bitline IT, 1C cell; an implementation employing a buried strap is proposed. Maximization of array density requires multiplexing bitlines to sense amps. © 1994 IEEE
S. Dhong, W.H. Henkels, et al.
VLSI Circuits 1989
R.V. Joshi, W. Hwang, et al.
International Symposium on VLSI Technology, Systems, and Applications, Proceedings
W.H. Henkels
IEEE Transactions on Magnetics
L.D. Jackel, W.H. Henkels, et al.
Applied Physics Letters