Joachim N. Burghartz, Mehmet Soyuer, et al.
IEEE Transactions on Electron Devices
A novel bipolar isolation structure with capability of significantly reducing collector-base capacitance and base resistance is presented. Partial SOI, with SOI surrounding the collector opening, can be used to reduce the collector window width in combination with any emitter-base self-aligned bipolar device structure, and in particular for device structures that feature sublithographic emitter width. Near-ideal transistor Gummel characteristics and a minimum ECL gate delay of 24 ps have been achieved with a nonoptimized lateral device layout, and simulations suggest that sub-20-ps delay at reduced switch current will be possible by using the optimized partial-SOI isolation structure. © 1992 IEEE
Joachim N. Burghartz, Mehmet Soyuer, et al.
IEEE Transactions on Electron Devices
Joachim N. Burghartz
ESSDERC 1997
Marco Bellini, Peng Cheng, et al.
SPIE International Symposium on Fluctuations and Noise 2007
Mehmet Soyuer, Joachim N. Burghartz, et al.
IEEE Journal of Solid-State Circuits