Optimized Silicon-Rich Oxide (SRO) Deposition Process for 5-V-Only Flash EEPROM Applications

Abstract

A process to deposit in-situ very-thin (< 10 nm) SiO2 films on top of a silicon-rich oxide (SRO) layer in a standard LPCVD reactor has been optimized. Polysilicon-gate MOS capacitors using this stacked dielectric have shown high tunneling current at low voltages and an extraordinary endurance to electrical stress. Indeed, capacitors with 7-nm LPCVD SiO2 on top of 10-nm SRO did not show any relevant shift on either the low or high portion of the I-V characteristic, after a fluence of more than 500 C / cm2 at J = 0.1 A / cm2. Our results add further support to the successful implementation of these stacked dielectric structures in a variety of nonvolatile memory devices. © 1993 IEEE