Publication
ISSCC 2013
Conference paper

Optical receivers using DFE-IIR equalization

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Abstract

Future computing systems will require increasingly high bandwidth to supply data to microprocessors, FPGAs, and other computational blocks [1,2]. Increasing data rate is a common solution, as I/O pad density is not scaling with bandwidth requirements. Copper interconnect has increasingly high loss with frequency, requiring complex, power-hungry equalization to overcome the channel response at high data rates. In contrast, optical interconnect can transport signals over long distances without complex equalization. Chip-to-chip optical interconnect will require sensitive, low-power, clocked receiver (RX) circuits that operate at high data rates. Conventional TIA-based RXs [1,2] require high power to maximize gain and minimize noise while maintaining high BW. A low-noise, low-BW, low-power TIA is combined with a 2-tap DFE to achieve high sensitivity in [3], but the data rate is 4Gb/s and limited dynamic range is demonstrated. Double-sampling architectures eliminate the TIA, replacing it with a large resistor [4] or a capacitive integrator [5], which decreases the front-end BW. The BW is equalized by double sampling, which is equivalent to a 2-tap FFE. However, the use of small sampling capacitors in [4,5] adds kT/C noise, limiting sensitivity. In this work, we demonstrate an optical RX with a large input resistance to maximize gain and sensitivity, while DFE with IIR feedback (DFE-IIR) [6] eliminates the resulting ISI with minimal added noise. © 2013 IEEE.

Date

29 Apr 2013

Publication

ISSCC 2013

Authors

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