Conference paper
Performance analysis of tapered gate in PD/SOI CMOS technology
W. Hwang, C.T. Chuang, et al.
VLSI-TSA 2001
A detailed study on the scaling property trench isolation capacitance for advanced high-performance bipolar applications is presented. It is shown that the trench isolation capacitance depends on the trench structure, particularly the trench bottom and the trench fill. The dependence of the trench isolation capacitance on the trench width is then analyzed for various commonly used trench structures. The impact on the scaled-down high-performance ECL circuits is presented. © 1990 IEEE
W. Hwang, C.T. Chuang, et al.
VLSI-TSA 2001
K. Kim, K. Das, et al.
International Journal of Electronics
C.T. Chuang, P.F. Lu
IEDM 1989
C.T. Chuang, P.F. Lu, et al.
International Journal of Electronics