Oxide breakdown model and its impact on SRAM cell functionality

Abstract

The influence of the oxide hard breakdown (HBD) in an SRAM cell on the performance of a circuit that includes the cell, together with the bit select circuit and sense amplifier for the read and write process of the cell, have been analyzed. The analysis of the impact of oxide HBD on this circuit has been performed through the variation of different parameters as the bitline differential voltage and the read and write delays of the cell for different levels of oxide HBD damage in the cell. The results show that oxide BD between gate and source of the NFETs of the SRAM cell seems to have more influence in the circuit performance than in other cell positions.