About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Conference paper
A high-speed low-power JFET pull-down ECL circuit
Abstract
A high-speed low-power ECL (emitter coupled logic) circuit with an active pull-down output stage that utilizes a ″free″ JFET (junction FET) available in any npn bipolar technology is described. The JFET pull-down output stage operates as a push-pull follower stage and enhances both the speed and load driving capability. Simulation results based on an 0.8-μm double-poly self-aligned bipolar technology indicate that the circuit with a typical loading at a power consumption of 1 mW per gate offers 24% improvement in the pull-down delay and 53% improvement in the load driving capability compared with the conventional ECL circuit.