Publication
IEEE T-ED
Paper

On the Perimeter Base Leakage of Double-Poly Self-Aligned p-n-p Transistors

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Abstract

It is shown that in the shallow junction formation for high-performance p-n-p devices, the perimeter E-B junction may be positioned inside the polysilicon due to insufficient boron dopants, causing excessive low-level base leakage current and current gain degradation. The I-V characteristic has an exp (qV/2kT) dependence consistent with carrier recombination at grain boundaries. Although the problem can be fixed by using a deep emitter drive-in, the resulting ac performance will be traded off due to increased emitter charge storage. The nonuniform lateral profile limits the minimum achievable emitter junction depth for useful p-n-p devices, which in turn makes thin-base formation more difficult. © 1992 IEEE

Date

01 Jan 1992

Publication

IEEE T-ED

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