Edward J. Nowak, Ingo Aller, et al.
IEEE Circuits and Devices Magazine
An NTL circuit with a charge-buffered active-pulldown emitter-follower stage is described. The circuit utilizes the diffusion capacitance of a charge-storage diode (CSD) as the coupling element between the common-emitter node of the switching transistors and the base of an active-pull-down n-p-n transistor to generate a large dynamic current for the pull-down transistor and to provide a speedup effect on the switching logic stage. Implemented in a 0.8-μm double-poly trench-isolated selfaligned bipolar process, unloaded gate delays of 12.8 ps/1.0 mW, 15.4 ps/0.71 mW, and 18.0 ps/0.53 mW have been achieved. © 1992 IEEE
Edward J. Nowak, Ingo Aller, et al.
IEEE Circuits and Devices Magazine
Mehmet Soyuer, James D. Warnock
IEEE Journal of Solid-State Circuits
Meng-Hsueh Chiang, Jeng-Nan Lin, et al.
SISPAD 2007
Ruchir Puri, Ching-Te Chuang
International Journal of Electronics