On-chip wiring design challenges for GHz operation

Abstract

It will be shown that system-on-chip needs to adopt and adapt the tools, understanding, and practices used for designing chip-to-chip interconnections. This involves optimization of length, cross section, use of buffers, repeaters and operating temperature. Better materials and hierarchical cross sections help improve performance. Designers have to learn to use controlled transmission-line structures and new computer aided design tools have to be developed to include inductive effects. Multivariable performance-driven routers are greatly needed. System designers need to understand the limitations affecting the sustainable risetimes (bandwidth) which will become the performance limiter for GHz operation.