3D integration is a promising technology for advancing the performance of semiconductors since it can provide higher density, faster speed and better power efficiency in a smaller form factor [1-3]. The Through Silicon Via (TSV) is an important component for achieving the benefits of 3D integrated semiconductors. However, depending on the temporary wafer bonding technology's behavior during processing at temperatures above 250°C, the TSV formation process can be limited. Process integration steps where high temperature tolerance is critical include PECVD, PVD, and solder reflow. In the case of PECVD, the difficulty and challenge is to obtain sufficient thin film insulator performance at low process temperatures because the quality of plasma-deposited insulating films is known to degrade as processing temperatures are reduced. Furthermore, stress builds up in the thinned wafer due to CTE difference in the various layers of films on the chips and the adhesive/carrier system must be able to control any movement induced by this stress. The thin wafer handling system from TOK called Zero Newton was used in this study. The Zero Newton system provides low stress bonding and debonding capabilities by utilizing perforated glass carriers with solvent dissolvable adhesives. By specially engineering the adhesives for use over higher temperature ranges, it is possible to deposit good quality insulating PECVD films and still debond the wafer from the temporary carrier without stress and without adhesive residue. The focus of this paper is to report on the development of a novel temporary adhesive with a temperature tolerance of up to 280°C for use during PECVD processing. Temporary adhesives can be made from various polymers but the thermal stability is a very important consideration in the selection process. Factors such as out-gassing and cross-linking affect the ultimate thermal budget of integration processing as well as the speed of dissolution during the debonding process. Two other important parameters that need to be considered include the glass transition point (Tg) of the adhesive, and a parameter we call the "softening point". We have found that the softening point needs to be sufficiently high in order to process CMOS-compatible wafers at high temperatures. Thinned wafers fabricated with TSVs and Cu damascene wiring layers can give rise to significant stress during processing. This stress can manifest itself as non-planarity or warpage in the wafer and in individual die. Thus, a temporary adhesive must not only provide bonding between a mechanical handler and the thinned wafer but also must constrain micro and macro level warpage in the wafer during processing. © 2010 IEEE.