Moderate-temperature anneal of 7-nm thermal SiO₂ in O ₂- and H₂O-free atmosphere: Effects on Si-SiO₂ interface-trap distribution

Abstract

A silicide anneal furnace, nominally oxygen and water free, has been used to anneal in the temperature range between 500 and 800 °C, in Ar or N 2, silicon/oxide structures having a dielectric layer (thermal SiO2) about 7 nm thick. Quasistatic current-voltage measurements have pointed out a dramatic increase of the interface traps after just a few minutes anneal at T=700 °C. To prove that such an increase on interface-trap concentration could be correlated to a very low oxygen and/or water content inside the anneal chamber, the same oxide films have been annealed, before metal deposition, under ultrahigh vacuum (UHV)(10-8 Torr) in the same temperature range and for the same time intervals. Electron paramagnetic resonance (EPR) analysis has shown an increase of the Pb(111) and Pb1(100) defect centers, leaving unchanged the density of P b0(100) defect centers. Experimental data on annealing efficiency and the strong similarity observed between results after anneals performed in the silicide anneal furnace and under UHV lend support to the idea that the cause of the Si-SiO2 interface degradation may be the Pb center reverse-passivation reaction. Also, EPR analysis has provided evidence of a different annihilation behavior of the Pb(111) and P b0(100) centers. Finally, the comparison between the time-zero breakdown distribution after anneal in a silicide anneal furnace and under UHV has shown that (i) the Si-SiO2 interface degradation is not a precursor step of a more complex reaction process leading to the loss of the oxide integrity; (ii) for a thin oxide layer (in our case less than 10 nm), the electrical activation of macroscopic defects during anneal under vacuum happens at temperature much lower than previously reported.